Normal Computing
0 open Forward Deployed Engineer roles at Normal Computing, plus 1 closed. Curated with comp bands.
On the board since Jul 2026 · no roles open right now
Our take
Why Normal Computing
The only FDE seat where you live inside SystemVerilog and UVM testbenches — a rare vertical almost no other forward-deployed engineer can touch.
- FDE type
- True forward-deployed
- Travel
- Medium
- Comp
- Competitive
- Stage
- Early-stage
A good fit if you're…
- Python / ML engineers (fine-tuning, evals, RAG, agentic patterns) willing to go deep on semiconductor verification
- People who want a vertical almost no other FDE can claim — chip design, not SaaS
- Candidates who can embed in customers' SystemVerilog and UVM environments, or learn to fast
- Those open to New York, SF, Copenhagen, Seoul or London and periodic customer travel
A 'frontier AI lab for silicon'
Normal Computing (founded 2022) builds Normal EDA, AI software for chip design that pairs large language models with formal logic — 'auto-formalization' — to compress design timelines the company says otherwise run years into months. CEO Faris Sbahi frames the near-term claim conservatively: roughly 2x faster custom silicon to market today. It sells into chipmakers directly rather than shipping a generic developer API.
What 'forward deployed' means here
You own Normal EDA inside a customer's environment: integrating it with their design flows and production codebases, diagnosing issues across the model, data and workflow, and carrying silicon-team constraints back to research. The surface area is chip verification — customers' SystemVerilog and UVM testbenches — which makes this specialized field engineering rather than a typical enterprise FDE motion.
What they actually want you to bring
Despite the hardware vertical, the posting asks first for strong Python and distributed-systems literacy plus real ML-stack depth — fine-tuning, evals, RAG, agentic patterns — and then a willingness to go deep on semiconductor verification. In practice that means an ML engineer who'll learn the chip world, or the rare chip-plus-ML hybrid, far more than a pure EDA veteran with no ML background.
Comp reflects a scarce skill blend
The board shows $180K-$325K, a wide band that mirrors how much the level depends on straddling ML and silicon. The ceiling is real for candidates who genuinely cross both worlds; the floor still rewards a strong ML engineer willing to go deep on verification. Expect the offer to track exactly how much of that rare overlap you bring.
The Carnot moonshot behind the day job
Separate from the EDA software, Normal's Carnot program taped out CN101 in 2025, which it calls the world's first thermodynamic computing chip, targeting up to 1,000x energy-efficiency gains for workloads like image and video generation. That's a potential, not a shipped result — but it signals the research depth behind the field role, with the hardware work part-funded by the UK's ARIA.
Why the footprint is this global
FDE seats span New York, San Francisco, Copenhagen, Seoul and London — unusually international for an early company, and a direct read on the customer base. Normal says it partners with more than half of the top ten semiconductor companies by revenue, which sit across the US, Europe and Asia, so the field org is being seeded near those customers from the start.
Questions candidates ask
Do I need to be a chip-design expert already?
Not necessarily. The posting leads with strong Python, distributed-systems and ML-stack experience, then a willingness to go deep on semiconductor verification — ideal for an ML engineer who'll learn the silicon world, or a rare ML-plus-chip hybrid.
Where are the roles based?
New York is primary, with seats also in San Francisco, Copenhagen, Seoul and London — tracking Normal's global chipmaker customers. Expect periodic travel to those customers.
What's the difference between Normal EDA and the Carnot chip?
Normal EDA is the AI chip-design software you'd deploy as an FDE. Carnot is a separate hardware program; its CN101 thermodynamic chip is R&D, not the product you'd be integrating.
How well funded is the company?
Well capitalized for its stage: a $50M round in March 2026 led by Samsung Catalyst Fund brought total funding above $85M, with investors including Micron Ventures and Eric Schmidt's First Spark Ventures.
Analysis updated 2026-10-09
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